Although in the following, mainly memory devices and their manufacturing method are explained as an illustrative example, the invention can be applied to a broad scope of semiconductor devices, including, but not limited to memories, logic and wireless applications. Since tilted implants are mainly used to define the properties of MOS transistors, a preferred field of application of the invention is, e.g., halo implants of transistors. For example, these transistors may be surrounded by a patterned area comprising patterns in which pattern densities are locally varying over the chip. However, the invention is not limited to DRAM. The tilted implants may even have other functions than the definition of halo implants, such as, e.g., the definition of contacts, the definition of single sided buried straps, contact implants and others. Descriptions in the later text citing the formation of a transistor structure are not meant to narrow the applicability of the invention.
Memory devices such as dynamic random access memories (DRAM), non-volatile memories and other well known memory devices generally comprise a memory cell array as well as a peripheral portion in which circuits for driving the memory cell array and for performing reading and writing operations are disposed. Usually, the circuits in the peripheral portion as well as each of the memory cells comprise transistors which are at least partially formed in a semiconductor substrate. Generally, each of these transistors comprises a first and a second source/drain region, a channel which is disposed between the first and second source/drain regions and a gate electrode. The gate electrode controls the conductivity of the channel. A transistor may further comprise a halo doped portion which is disposed between the channel and the first and second source/drain regions. The halo doped portion is doped with a dopant of a conductivity type which is opposite to the conductivity type of the first and second source/drain regions. This halo doped portion suppresses short-channel effects.
Usually, for forming an array transistor or peripheral transistor, first, the gate electrodes are formed by patterning a conductive layer stack. Thereafter, doping steps are performed for defining the first and second source/drain portions. In particular, this doping step usually is performed as an ion implantation step. During this ion implantation step, the gate electrodes as well as a patterned photoresist layer are taken as an implantation mask so that the ions are implanted only in predetermined substrate portions.
To illustrate the effects typically visible when performing a tilted implant on a wafer having protruding portions of varying density over a wafer surface, FIG. 1 shows an exemplary cross-sectional view of a semiconductor substrate 1. On the surface 10 of the semiconductor substrate 1, gate electrodes 2 as an example of protruding portions are disposed. In particular, the gate electrodes 2 have been defined by a conventional method, in which, first, a layer stack comprising at least one conductive layer, is deposited and patterned in accordance with the circuitry to be formed. On top of the resulting surface, thereafter, a photoresist layer 34 is deposited and patterned so that portions of the substrate surface 10 are uncovered. Usually, after correspondingly patterning the photoresist layer 34, a tilted ion implantation step is performed taking the photoresist mask 34 as well as the gate electrodes 2 as a shadowing mask.
Thereby, the halo doped portion 42 as is shown in FIG. 1 is defined. As can be gathered from FIG. 1, the lateral extent of the doped portion depends on the height h of the photoresist layer 34.